This invention relates to a semiconductor device which is incorporated in an LSI circuit or the like.
A conventional semiconductor device of the type described comprises a large number of electronic elements, such as flip-flops, and the like, and a clock driver which delivers clock signals to the electronic elements through a wiring pattern between the electronic elements and the clock driver.
It is preferable that the clock signals are delivered to all of the electronic elements without any difference of a delay time, namely, a delay time difference. Such a delay time difference is generally called a clock skew. However, it is practically difficult to completely get rid of the clock skew because of differences of lengths of the wirings.
In order to reduce such a clock skew, it has recently been proposed that the wiring pattern is formed into a lattice-shape. Such a lattice-shaped wiring pattern is exemplified in Unexamined Japanese Patent Publication No. Sho 63-107316, namely, 107316/1988.
In the interim, it is a recent trend that an integration scale in the semiconductor device becomes larger and larger and that a frequency of the clock signals becomes higher and higher.
Under the circumstances, it is inevitable that the wiring pattern becomes long. Furthermore, it sometimes happens that an error operation is caused to occur by a timing error which results from the above-mentioned clock skew.
The clock skew becomes large with an increase of the integration scale, which causes the error operation to frequently occur.
Although consideration is made in the above-referenced publication only about the clock skew which occurs in a single wiring pattern, such a clock skew might become serious when a semiconductor device comprises a plurality of wiring patterns in the form of wiring blocks.